The invention relates to an addressing system for efficiently fetching a block of information into cache memory. More particularly, the invention relates to a memory address modification system for dynamically testing for local inhibit signals from portions of an interleaved memory and altering the sequence in which words of a cache block are fetched in response to the inhibit signals.
Designers of digital computers have recognized that the central processing unit of a digital computer in most instances can process information at a much higher rate than the information can be transferred to and from main memory. As a result, it is well known to those skilled in the art to employ a high speed buffer or cache memory adjacent the central processing unit to speed up the transfer of information to and from the processing unit during execution.
Typically, the high speed buffer or cache memory is relatively small and stores segments or blocks of information which are currently being used by the processor unit. The processor unit fetches words used as instructions or operands from the cache memory. Since the cache memory is small, at times the processor unit may attempt a fetch and receive a cache miss signal indicating that the cache does not contain the information to be fetched by the processor unit. In other words, the cache indicates that there is no cache hit for the fetch operation. At that point, the cache memory initiates a fetch operation to retrieve a block of information containing the missing word from main memory.
In some high performance computer systems, main memory is interleaved and spatially distributed across a system bus. In such a conventional system when a cache miss is indicated, the cache memory will initiate memory read operations for the missing block. One scheme which is commonly followed would require that the lowest order word in the block is fetched first followed by the next lowest and so on until all words in a particular block have been transferred into the cache memory from the main memory. In the event that one of the words to be fetched is unavailable, in other words, the portion of the main memory in which it is stored is temporarily inhibited, prior art cache memories typically wait until the inhibit is cleared, also causing the processor unit to wait. As a result, the processor unit functions at the same speed as a relatively slow speed portion of the interleaved memory. This can constitute a significant performance disadvantage.
What is needed then, is a system for improving the efficiency of memory read operations by a cache memory in order to maximize the efficiency of the attached processor unit.